NXP, TSMC bring embedded MRAM to automotive MCUs ...

Jan 09, 2024

According to NXP, MRAM can update 20MB of code in about 3 seconds – much faster than todays's standard technology, Flash memories, that take about 1 minute for the same amount of data. This minimizes the downtime associated with software updates and enables carmakers to eliminate bottlenecks that arise from long module programming times, explains Ed Sarrat, Senior Director of Product Management, Automotive MCUs for NXP. In addition, MRAM provides a highly reliable technology for automotive mission profiles by offering up to one million update cycles, 10x greater than flash and other emerging memory technologies such as RRAM. This feature set makes MRAM ideal, if not a requirement for the upcoming age of Software Defined Vehicles (SDVs).

Comparison of MRAM, Flash and RRAM properties. © NXP

Besides faster writing speed compared to flash, the entire access process to memory content is greatly simplified with MRAM, explains Sarrat. In contrast to Flash, with MRAM there is no erase step necessary before writing into a memory cell. Writing can be done in one single step as opposed to five consecutive steps with Flash. What's more, with 1 million write/erase cycles, MRAM can be used much like today's EEPROM – but unlike the latter, it can be integrated on chip and thus eliminates the need for off-chip EEPROM. Similarly, external datalogging Flash memory can be omitted. Plus, it reduces the effort for ‘keep alive’ circuitry as a protection measure against in-car brownout. Also, the MRAM circuitry can run on the standard chip voltage of 1.8V while Flash needs on-chip circuitry to generate the 9V required for the write process.

MRAM also reduces the software complexity. Because with Flash, the memory location must be erased before every write, no erase scheduling routines are required, which simplifies driver and boot loader software. In certain cases – such as access to lookup tables, calibration data and similar infrequently updated data sets, MRAM can replace SRAM, freeing up valuable SRAM capacity for alternate functions, explained Sarrat.

Through the collaboration with TSMC, NXP can implement MRAMs in 16nm. "We are not announcing a specific product," clarifies NXP's Sarrat. "Instead this announcement is about our collaboration with TSMC." Nevertheless, the collaboration aims at implementing real products sooner or later. First products can be expected in the first half of 2025.

www.nxp.com

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